Error correction scheme for memory

ABSTRACT

An embedded DRAM ECC architecture for purging data errors. The embedded DRAM ECC architecture is based upon a two-dimensional linear parity scheme, and includes a plurality of memory blocks and a parity block. Each memory block includes additional columns for storing row parity bits, and the parity block stores column parity bits. A row parity circuit coupled in parallel to an existing local databus of each memory checks the parity of the local databus bits against a row parity bit during a refresh or read operation to identify parity failure. Identification of the incorrect bit of the word is achieved by iteratively transferring the data of the local databus of each memory block onto an existing global databus, and checking the parity across the global databus with a column parity circuit. When global databus parity failure is detected, all bits of the global databus are inverted to purge the incorrect bit from the memory block via the local databus.

This application claims priority from U.S. Application No. 60/429,556filed Nov. 29, 2002, the contents of which are herein entirelyincorporated by reference.

FIELD OF THE INVENTION

The present invention relates generally to memory devices. Moreparticularly, the present invention relates to error detection andcorrection for embedded DRAM memories.

BACKGROUND OF THE INVENTION

Modern PDA products and combination cell phone/PDA products, referredfrom this point forward as portable devices, require substantial amountsof memory. While many portable devices are assembled with multiplediscrete components, cost and performance pressures point to single-chipsystem on chip (SoC) implementations as the optimal solution. Suchapplications, like most other semiconductor devices, tend to be built onhigh-volume standard processes, such as standard logic processes to keepfabrication costs under control.

For consumers, battery life of portable devices is a primary concern,hence power consumption of the portable device should be kept as low aspossible. Moreover, these portable devices preferably operate on verylow power in standby mode. While many functions can be shut down instandby mode, memory cannot be lost. Thus the optimal approach is to usesome form of non-volatile memory. Unfortunately, Flash memory is notpresently compatible with standard logic processes, and ferro-electricmemories are not presently a high-volume standard process.

Therefore, the most promising and practical memory for portable devicesis DRAM, and more specifically embedded DRAM (eDRAM) for SoCimplementations. There is already a clear trend for embedding DRAMcompatible with standard logic processes into SoC products. Theadvantages are demonstrated in products that can be made smaller,consume less power while operating faster than their discrete componentsystem counterparts. Although SRAM memory can be used, SRAM memoryarrays consume more silicon area than a DRAM memory array of the samedensity.

As known to those of skill in the art, DRAM requires periodic refreshingof its data, which contributes to power consumption. Hence portabledevices having eDRAM can benefit if the period between refreshoperations is extended as much as possible. In the standby mode of theportable device, battery life can be extended by minimizing refreshpower consumption.

Unfortunately, the reliability of an embedded DRAM to operate properlygenerally requires some minimum capacitance value for memory cell chargestorage. Reliability in the memory context commonly refers to theability of a memory cell to retain the logic level written to it. Thelogic state of a DRAM memory cell can change due to leakage of itsstored charge over time, or due to random alpha particle hits, either ofwhich can result in system errors. Furthermore, different DRAM cells canleak charge at different rates. The refresh interval is thus set toaccommodate the fastest leaking DRAM cell, and cannot be overly extendedto save power.

Data reliability is a problem that has been addressed in thetelecommunications and mass storage fields, where wireless transmissionsare susceptible to signal degradation and mass storage media such ascompact discs and computer hard disk drives routinely encounter readerrors. The detection and correction of “bad bits” of data to improvereliablity is achieved through Error Correction Coding (ECC) techniques.Many ECC techniques and coding schemes are well known in the art, andtherefore do not require further description.

Accordingly, ECC has been used in memory systems, and over the yearspapers have appeared describing a variety of memory chips including thefunction within the chip. Most are based on “Hamming” codes, ModifiedHamming, or Reed-Solomon codes. The additional silicon area consumptionand impact upon performance due to added overhead limit such chips tovery specific applications, and hence have not seen widespreadcommercial use. These issues become more serious, when seeking to applyECC to a compiled embedded memory where the size and word length of thememory are, by definition, variable. Hence an ECC scheme tailored forone particular embedded memory configuration may not apply to anembedded memory having a different configuration. Those of skill in theart should understand that a compiled embedded memory is produced withthe aid of computer software tools through which designers can specifymemory bank sizes, the number of memory banks, and other parameters, tosuit a specific application.

A published ECC scheme for standard memory devices that showed somepromise was a two-dimensional linear parity encoding scheme. FIG. 1illustrates the principle of two-dimensional linear parity encoding witha 16 by 16 memory cell array. To simplify the illustration, wordlines,bitlines or peripheral circuits such as bitlines and column accessdevices are not shown. Memory array 20 is composed of memory cellsarranged in rows and columns, where each square 22 represents a memorycell. This configuration is well known in the industry. One additionalrow and column of memory cells are added to memory array 20, where theadditional row is a parity row 24 and the additional column is a paritycolumn 26. Hence, if a rectangular array of memory cells can be checkedfor parity in orthogonal directions, the intersection of the failinglines defines a bad bit. In the example shown in FIG. 1, the row of abad bit 28 can be identified by checking the parity of its associatedrow of memory cells against the parity column bit 30 in the same row.Correspondingly, the column of bad bit 28 can be identified by checkingthe parity of its associated column against the parity row bit 32 in thesame column. Therefore bad bit 28 can be identified for correction ofits data. Moreover, any two bad bits in the array can be detected andcorrected so long as no two bad bits appear on the same line.

Known methods for implementing the two-dimensional linear parityencoding scheme for DRAM were found to be clumsy, adding excessiveamounts of wide bussing as well as the ECC circuitry itself. Althoughthe increase in chip size due to the added parity rows and columns isunavoidable, the increase due to the additional wide bussing and ECCcircuitry further reduced the cost effectiveness and advantages ofadding the error correction capability.

Another problem inherent to most memory ECC schemes is their inabilityto correct, or purge, the memory cell identified with the faulty data.If the data is corrected only at read out, then the memory array willaccumulate bad bits over time. Although some schemes then purge thememory cell with corrected data, they can do so only during a readaccess. Hence bad bits can accumulate in between read access operations,especially if the interval between read access operations is long.Naturally, error correcting at read out also impacts device performancedue the additional logic overhead of the ECC circuits.

It is, therefore, desirable to provide a memory ECC architecture thatoccupies minimal silicon chip area, and performs error detection andpurging with minimum impact upon device performance.

SUMMARY OF THE INVENTION

It is an object of the present invention to obviate or mitigate at leastone disadvantage of previous ECC schemes. In particular, it is an objectof the present invention to provide an error detection and purgingsystem for a memory that occupies a minimum silicon area, and canautomatically detect and purge errors in a self-contained manner suchthat detection and purge operations are transparent to the user orexternal system.

In a first aspect, the present invention provides an error detectionsystem for a memory. The error detection system includes a memory blockfor storing a data word and a corresponding row parity bit, and a rowparity circuit for receiving the data word and the corresponding rowparity bit from the memory block in response to a memory block accessoperation, for comparing parity of the data word against thecorresponding row parity bit. The row parity circuit generates an activelocal parity fail flag in response to parity failure.

In an embodiment of the present invention, the error detection systemfurther includes a local data I/O circuit for coupling the data wordbetween the memory block and a global databus, and for coupling thecorresponding row parity bit between the memory block and the row paritycircuit. The row parity circuit can include a serial parity chain forreceiving the data word from the local data I/O circuit and forproviding a parity output corresponding to parity of the local data, anda sense circuit for receiving the parity output and the correspondingrow parity bit. The row parity circuit provides the active local parityfail flag if the logic state of the parity output and the logic state ofthe local row parity bit mismatch. In an aspect of the presentembodiment, the serial parity chain includes an even parity line drivento a first logic level at one end thereof, and an odd parity line drivento a second logic level at one end thereof. The parity output isprovided from the other end of the even parity line, and each paritycircuit includes cross-over transistors for coupling the parity outputto one of the first and second logic levels. In a further aspect of thepresent embodiment, the sense circuit can include a cross-coupled latchfor receiving and latching the parity output, and a comparator circuitfor comparing the latched parity output to the local row parity bit.

In other aspects of the present embodiment, the comparator circuitincludes an exclusive OR gate, the sense circuit includes switchingmeans for coupling the latched parity output to the memory block duringa write operation, the serial parity chain is segmented into at leasttwo serially connected sub-parity circuits, and the memory blockincludes one of redundant rows and columns, and corresponding redundancycircuits.

In another embodiment of the present invention, the error detectionsystem further includes a parity block and a column parity circuit. Theparity block stores a column parity word where each bit of the columnparity word represents column parity for a corresponding bit position ofthe data word. The column parity circuit is coupled to the local dataI/O circuit and the parity block for receiving the data word and thecolumn parity word, and for comparing column parity of each bit positionof the data word to a corresponding bit of the column parity word inresponse to the active local parity fail flag. The column parity circuitinverts data of each bit position of the data word that fails columnparity. In an aspect of the present embodiment, the memory block, therow parity circuit, the parity block and the column parity circuit areintegrated in an embedded DRAM.

In an aspect of the present embodiment, the parity block has aconfiguration identical to that of the memory block, and a parity blockdata I/O circuit for coupling the word of column parity bits between theparity block and the column parity circuit. The column parity circuitcan include a multiplexor circuit, a parity block multiplexor circuit, aparity evaluator circuit, and a global dataline inverting circuit. Themultiplexor circuit is coupled between the local data I/O circuit andthe global databus for receiving the bits of the data word and foriteratively providing each bit of the data word to the global databus.The parity block multiplexor circuit is coupled to the parity block dataI/O circuit for receiving the bits of the column parity word and forproviding one bit of the column parity word in each iteration. Theparity evaluator circuit is coupled to the global databus for receivingthe one bit of the column parity word, and for comparing parity of theglobal databus to the one column parity bit in each iteration andgenerating an active global parity fail flag in response to columnparity failure. The global dataline inverting circuit receives and theninverts data of the global databus in response to the active globalparity fail flag.

In embodiments of the present aspect, the multiplexor circuit and theparity block multiplexor circuit can each include a counter forcontrolling operation thereof, the parity evaluator circuit can includea serial parity chain and a sense circuit, and the global datalineinverting circuit can include a flip-flop. The serial parity chain iscoupled to the global databus for providing a parity outputcorresponding to parity of the global databus. The sense circuitreceives the parity output and the one bit of the column parity word,for providing the active local parity fail flag if the logic state ofthe parity output and the logic state of the one bit of the columnparity word mismatch. The flip-flop has an input coupled to a globaldataline, an output coupled to a complementary global dataline, acomplementary output coupled to the global dataline, and a clock inputfor receiving the active global parity fail flag.

In yet another embodiment of the present invention, the error detectionsystem further includes a column parity check circuit for selectivelychanging bits of the column parity word on the global databus in a writeoperation, for writing a new word to an address of the data word storedin the memory block. The column parity check circuit includes a paritycomparison circuit and a parity inverting circuit. The parity comparisoncircuit stores the data word and the new word and compares each bitposition of the stored data word to each corresponding bit position ofthe stored new word. The parity comparison circuit provides a mismatchflag signal for each bit position having mismatching logic states. Theparity inverting circuit is coupled to the global databus for receivingthe mismatch flag signals, and for inverting the logic state of theglobal dataline pairs in response to the corresponding received mismatchflag signals.

In further embodiments of the present invention, the memory can be aDRAM, an SRAM, or an FeRAM, and the memory block access operation can bea DRAM refresh operation or a data purge operation.

In a second aspect, the present invention provides a method of detectingand purging bit errors in a memory. The method includes executing a readoperation to read a data word and corresponding row parity bit from amemory block of the memory, comparing row parity of the data wordagainst the corresponding row parity bit and generating a row parityfail flag in response to row parity failure, comparing column parity ofeach bit of the data word against a corresponding bit of a column parityword stored in a parity block of the memory, in response to the rowparity fail flag, and inverting bits of the data word that fail columnparity.

In an embodiment of the present aspect, the step of executing includessuppressing the data word from global I/O circuits and providing thedata word and the corresponding row parity bit to a local databus.

In other embodiments of the present aspect, the step of comparing rowparity can include executing a row parity check of the local databusagainst the corresponding row parity bit, the step of comparing columnparity can include iteratively multiplexing bits of the data word fromthe local databus to a corresponding global databus line in response torow failure, the step of comparing column parity can include executing acolumn parity check of the global databus against a corresponding columnparity bit in each iteration, and the step of comparing column paritycan include inverting the data bits of the global databus if columnparity failure is detected in each iteration.

In further embodiments of the present aspect, the step of inverting caninclude inverting the data bit of a local databus line coupled to one ofthe global databus lines for purging the bit error of the data wordstored in the memory block, and the step of iteratively multiplexing caninclude selectively activating column access transistors for coupling adifferent local databus line to the corresponding global databus line ineach iteration. The step of selectively activating can includeincrementing a counter to address and activate a different column accesstransistor in each iteration, and maintaining activation of the columnaccess transistor corresponding to the memory block having row parityfailure. In yet further embodiments of the present aspect, thebackground read operation can include a refresh operation or a datapurge operation.

In a third aspect, the present invention provides an error detection andpurging system for a memory. The system includes a plurality of memoryblocks for storing data words and corresponding row parity bits, one ofthe memory blocks being a parity block for providing a column parityword, a local data I/O circuit coupled to each memory block fortransferring the data words to global datalines, a row parity circuitand a column parity circuit. The row parity circuit is coupled to thelocal data I/O circuit of each memory block for receiving the data wordsand the corresponding row parity bits in a memory block accessoperation, and compares parity of the data words against thecorresponding row parity bits for generating a corresponding activelocal parity fail flag in response to row parity failure. The columnparity circuit is coupled to all the local data I/O circuits, the globaldatabus, and the parity block for receiving the data words and thecolumn parity word. The column parity circuit iteratively transfers abit from each of the data words to a different global dataline forcomparing parity of the global datalines to a corresponding bit of thecolumn parity word. The column parity circuit then inverts data of theglobal databus in response to column parity failure in each iteration.

In an embodiment of the present invention, each row parity circuit caninclude a serial parity chain for receiving the data word from the localdata I/O circuit and for providing a parity output corresponding toparity of the data word, and a sense circuit for receiving the parityoutput and the corresponding row parity bit, for providing the activelocal parity fail flag if the parity output and the corresponding rowparity bit mismatch. The serial parity chain can include an even parityline driven to a first logic level at one end thereof, and an odd parityline driven to a second logic level at one end thereof, where the parityoutput is provided from the other end of the even parity line, and eachparity circuit includes cross-over transistors for coupling the parityoutput to one of the first and second logic levels. The sense circuitcan include a cross-coupled latch for receiving and latching the parityoutput, and a comparator circuit for comparing the latched parity outputto the local row parity bit. The comparator circuit can include anexclusive OR gate.

In another embodiment of the present invention, each memory blockincludes one of redundant rows and columns, and corresponding redundancycircuits.

In yet another embodiment of the present invention, the parity block hasa configuration identical to that of each memory block, and a parityblock data I/O circuit for coupling bits of the column parity word tothe column parity circuit.

In an aspect of the present embodiment, the column parity circuit caninclude a multiplexor circuit, a parity block multiplexor circuit, aparity evaluator circuit, and a global dataline inverting circuit. Themultiplexor circuit is coupled between each local data I/O circuit andthe global databus for receiving the bits of the data word in paralleland for iteratively providing each bit of the data word to the globaldatabus. The parity block multiplexor circuit is coupled to the parityblock data I/O circuit for receiving the bits of the column parity wordin parallel and for providing one bit of the column parity word in eachiteration. The parity evaluator circuit is coupled to the global databusfor receiving the one bit of the column parity word, where the parityevaluator circuit compares parity of the global databus to the onecolumn parity bit in each iteration and generates an active globalparity fail flag in response to column parity failure. The globaldataline inverting circuit receives and inverts data of the globaldatabus in response to the active global parity fail flag. Themultiplexor circuit and the parity block multiplexor circuit can eachinclude a counter for controlling operation thereof, and the globaldataline inverting circuit can include a flip-flop having an inputcoupled to a global dataline, an output coupled to a complementaryglobal dataline, a complementary output coupled to the global dataline,and a clock input for receiving the active global parity fail flag.

In another aspect of the present embodiment, the error detection andpurging system further includes a column parity check circuit forselectively changing bits of the column parity word on the globaldatabus in a write operation, for writing a new word to an address ofthe data word stored in the memory block. The column parity checkcircuit includes a parity comparison circuit and a parity invertingcircuit. The parity comparison circuit stores the data word and the newword and compares each bit position of the stored data word to eachcorresponding bit position of the stored new word. The parity comparisoncircuit provides a mismatch flag signal for each bit position havingmismatching logic states. The parity inverting circuit is coupled to theglobal databus for receiving the mismatch flag signals and for invertingthe logic state of the global dataline pairs in response to thecorresponding received mismatch flag signals.

In a fourth aspect, the present invention provides a method for writingrow and column parity bits to a memory system in a write operation, thememory system having a memory block for storing a data word and acorresponding row parity bit, and a parity block for storing columnparity bits. The method includes latching a stored data word read outfrom an address to which a new data word is to be written, writing thenew data word to the address and generating a corresponding row paritybit, comparing data between each bit position of the stored data wordand the new word, and inverting the column parity bits corresponding tomismatching bit positions.

In embodiments of the present aspect, the step of latching includesreading the stored data word onto a global databus, and the step ofwriting includes latching the new data word.

In another embodiment of the present aspect, the step of invertingincludes reading the column parity bits onto a global databus andinverting the column parity bits of the global databus that correspondto bits of the stored data word that mis-match bits of the new dataword.

In yet another embodiment of the present aspect, the method furtherincludes a memory initialization step prior to the step of latching. Thememory initialization step includes writing preset logic values tomemory cells of an activated wordline, reading out the preset logicvalues for latching by bitline sense amplifiers, and activating allwordlines of the memory block to write the latched preset logic valuesthereto. In aspects of the present embodiment, the step of readingincludes disabling bitline precharge and equalize circuits after thepreset logic values are latched by the bitline sense amplifiers, and thestep of activating includes iteratively activating individual wordlinesby addressing each wordline with a refresh counter. Multiple wordlinesor all the wordlines can be simultaneously activated. The activatedwordline can include a master wordline and the step of writing includesactivating all column access devices to write the preset logic value toall the memory cells coupled to the master wordline.

Other aspects and features of the present invention will become apparentto those ordinarily skilled in the art upon review of the followingdescription of specific embodiments of the invention in conjunction withthe accompanying figures.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention will now be described, by way ofexample only, with reference to the attached FIGS., wherein:

FIG. 1 is a simplified illustration of a typical memory array;

FIG. 2 is a block diagram of a typical memory architecture;

FIG. 3 is a circuit schematic of the second stage column access block ofFIG. 2;

FIG. 4 is a block diagram of the ECC architecture according to anembodiment of the present invention;

FIG. 5 is a circuit schematic of the local parity circuit of FIG. 4;

FIG. 6 is a circuit schematic of the sense circuit shown in FIG. 5;

FIG. 7 is a circuit schematic of the barrel shift decoder/multiplexorcircuit shown in FIG. 4;

FIG. 8 is a circuit schematic of the decoder circuit shown in FIG. 7;

FIG. 9 is a circuit schematic of the global parity circuit shown in FIG.4;

FIG. 10 is a circuit schematic of the global databus inverting circuitshown in FIG. 4;

FIG. 11 is a flow chart showing a method of error detection and purgingaccording to an embodiment of the present invention;

FIG. 12 is a flow chart showing a method of initializing a memoryaccording to an embodiment of the present invention;

FIG. 13 is a flow chart showing a method of generating and writing rowand column parity bits according to an embodiment of the presentinvention; and,

FIG. 14 is a circuit schematic of a column parity check circuitaccording to an embodiment of the present invention.

DETAILED DESCRIPTION

An embedded DRAM ECC architecture for purging data errors is disclosed.The embedded DRAM ECC architecture is based upon a two-dimensionallinear parity scheme, and includes a plurality of memory blocks and aparity block. Each memory block includes additional columns for storingrow parity bits, and the parity block stores column parity bits. A rowparity circuit coupled in parallel to a local databus of each memorychecks the parity of the local databus bits against a row parity bitduring a refresh or read operation in order to identify row parityfailure for the word. Identification of the incorrect bit of the word isachieved by serially shifting the data of the local databus of eachmemory block onto a global databus, and checking the column parityacross the global databus with a column parity circuit. When globaldatabus parity failure is detected, all bits of the global databus areinverted to purge the incorrect bit from the memory block via the localdatabus.

In addition to detecting and purging bit failures, the presentlydisclosed ECC architecture can generate and write row and column paritybits as data words are written to the memory blocks. A method of rapidinitialization of the cells of the memory blocks using an existingrefresh counter prior is also disclosed. Therefore, the presentlydisclosed ECC architecture for purging data errors is a fullyself-contained, autonomous system that does not require externalprocessing of parity data from another system such as an off chipmicrocontroller or an on chip processing block

Prior to the discussion of the ECC architecture embodiments of thepresent invention, a common DRAM array is described below to providecontextual background for the upcoming description of the ECCcomponents.

FIG. 2 is a block diagram illustrating the common components of a DRAMarray. The layout of the memory blocks represents the conceptualarchitecture and is not intended to represent the practical layout ofthe device. Memory array 50 comprises of n memory blocks 52, where n isan integer number greater than 1. Each memory block 52 includes a localdata I/O circuit consisting of an associated first stage column accessdevices 54, local databus 56, and second stage column access devices 58.Each memory block 52 consists of memory cells, such as DRAM cells forexample, arranged in rows and columns, where each row of cells iscoupled to a wordline and each column of cells is coupled to a bitline.Each set of first stage column access devices 54 selectively couples apredetermined number of bitlines to the local databus 56, and each setof second stage column access devices 58 can be selectively enabled, oractivated, to couple their respective local databus 56 to global databus60. Additional spare rows and columns of memory cells can be included ineach memory block 52 to replace those rows or columns of memory cellsthat are found to be defective. Accordingly, the associated redundancycircuitry required for disabling the defective rows and columns,enabling a spare row or column, and addressing the spare row or columnwould be included in the memory device. Such redundancy schemes are wellknown in the art. Although not discussed or shown, those of skill in theart will understand that memory array 50 includes standard circuits toenable proper operation of the memory, but are not shown in FIG. 2 tosimplify the schematic. These standard circuits can include input-outputbuffers, row and column decoders, and pitch limited peripheral circuitssuch as row drivers and bitline sense amplifiers for example. It shouldbe apparent to those of skill in the art that local databus 56 andglobal databus 60 include a predetermined number of pairs ofcomplementary datalines.

An example of a possible configuration of memory array 50 follows.Memory array 50 is divided into 16 memory blocks 52, where each memoryblock 52 has columns divided into 32 groups consisting of 4 columns pergroup. A master wordline is coupled to corresponding wordlines of eachmemory block 52 for simultaneous activation of the same logical wordlinein one or more of the memory blocks 52. There can be any desired numberof wordlines in memory blocks 52. The first stage column access devices54 perform a 1 of 4 column select in each group to populate 32 localdatabus line pairs with data. The second stage column access devices 58perform a 1 of 16 block select to couple all 32 local databus line pairsof one memory block 52 to 32 global databus line pairs of GDB 60.Naturally, the first and second stage column access devices arecontrolled by well known column decoder circuits.

To read data from memory array 50, a master wordline is activated andmemory cells coupled to each wordline segment of the master wordlinedrive their respective bitlines, or column, with their stored data. Oncesensed by bitline sense amplifiers, the first stage column accessdevices 54 couple selected bitlines to the local databus 56. The secondstage column access devices 58 then selectively couple the local databus56 of one memory block 52 to the global databus 60. The global databus60 then carries the data to other circuits of the system. The bitlines,local databus and global databus can be precharged after the readoperation is completed or prior to the next read operation.

The relative independence from precise array and word sizes in thepreviously described DRAM memory array 50 makes it attractive forembedded DRAM devices, such as application specific integrated circuits(ASICs). Incorporating known DRAM schemes such as the use of segmentedwordlines and wide databus architectures allows for an attractiveimplementation of two-dimensional parity. According to an embodiment ofthe present invention, the inherent wide local and global databus of amemory array can be advantageously used for parity checking in additionto standard data read and write operations.

FIG. 3 is an example of a circuit implementation of second stage columnaccess devices 58 shown in FIG. 2. Two second stage column access deviceblocks 58, one associated with a respective memory block 52, are shown.Each second stage column access device block 58 includes a plurality ofcolumn access transistors 62 for coupling a local databus line to aglobal databus line 64. Although only one local databus line is shownconnected to one column access transistor 62, it should be understood bythose of skill in the art that each column access transistor 62represents a pair of transistors coupled to a true and a complementarydatabus line. The true and complementary local databus lines arelabelled as LDB0/*, LDB1/* etc. Preferably, each global databus line 64includes a pair of individual complementary databus lines, having thesame naming convention as the local databus lines. In the presentexample, the column access transistors 62 of the same second stagecolumn access device block 58 couple one pair of local databus lines toa pair of global databus lines 64. In the present scheme, each secondstage column access device block 58 is controlled by a single columnselect signal to simultaneously couple all its local databus lines tothe global databus lines. Hence only the data from one memory block 52is coupled to the global databus lines 64. It is well understood thatthe number of column access transistors, local and global databus linesdepends upon the specific memory configuration, and that standard columndecoder circuits generate the appropriate column access control signalsYA0 to YAi. For example, when YA0 is at the high logic level, LDB0/* toLDBi/* are coupled to GDB0/* to GDBi/*.

FIG. 4 is a block diagram showing an error detection and purging memorysystem 100 according to an embodiment of the present invention. Thememory array includes the same components as those shown in FIG. 2, butnow includes additional elements for enabling error detection andcorrection. These include parity columns 102, a parity block 110, a rowparity circuit coupled in parallel to the local data I/O circuit of eachmemory block, and a column parity circuit coupled to all the local dataI/O circuits and the global databus. The row parity circuit includes aparity evaluator circuit 104, while the column parity circuit includesbarrel shift decoder/multiplexor circuits 106 and 107, a counter 108, aparity evaluator circuit 112, a global databus inverting circuit 114,and a column parity check circuit 116. ECC memory system 100 candetermine row parity failure for a word being read out or refreshedthrough the local databus lines, meaning that the system has identifieda word containing at least one bad bit. The position of the bad bit isidentified through the global databus lines and corrected by invertingall the bits of the global databus lines. Control circuits ensure thatonly the local databus line corresponding to the identified bad bitposition remains coupled to a corresponding global data bus line. Thusthe corrected bad bit of the word can be rewritten back to memory. Thepresently disclosed error detection and purging system for memory doesnot require wide bussing for transferring corrected data back to thememory blocks, hence minimizing silicon area occupied by memory system100. Standard row and column redundancy can be implemented in memorysystem 100 without little to no additional design overhead since errordetection and correction, according to the embodiment of the presentinvention, is performed upon the local and global databuses.

Each memory block 52 now includes an additional set of columns 102,called parity columns for storing row parity bits. A parity bit databusPDB, carries a bit of data from the parity columns to a parity evaluatorcircuit 104. In FIG. 4, the LDB is denoted as having i pairs of localdatabus lines, where i pairs of local databus lines carry normal data,while the PDB bus is an additional pair of local databus lines forcarrying one row parity bit.

The parity evaluator circuit 104 is coupled in parallel to the localdatabus LDB for performing an exclusive OR function across the localdatabus, and comparing the result to the logic state of the row paritybit provided by the parity bit databus PDB. In otherwords, parityevaluator circuit 104 detects the presence of a bad bit in the word, butdoes not indicate the bit position of the bad bit. The barrel shiftdecoder/multiplexing circuit 106 is provided for executing a barrelshift of data from the local databus of each memory block to the globaldatabus GDB. The counter 108 provides sequential address information tothe barrel shift decoder/multiplexing circuit 106 of each memory block52 for serially coupling each of its local databus lines to one globaldatabus line.

Parity block 110 is at least the same size and configuration as eachmemory block 52 for storing column parity bits. The parity block 110 hasits own set of first stage column access devices 58, local databus LDB,parity evaluator circuit 104, second stage column access devices 54 andbarrel shift decoder/multiplexing circuit 107. The components associatedwith parity block 110 function in the same way as the components ofmemory blocks 52, with the same logical wordline as the memory blocksbeing activated simultaneously with activation of a master wordline. Thebarrel shift decoder/multiplexing circuit 107 associated with the parityblock 110 barrel shifts data from its local databus to the parityevaluator circuit 112, which is also coupled in parallel to the globaldatabus GDB.

Since barrel shift decoder/multiplexing circuits 106 and 107 operatesequentially, counter 108 can provide the appropriate addressing signalsto barrel shift decoder/multiplexing circuits 106 and 107. As analternative implementation, each barrel shift decoder/multiplexingcircuit 106 and 107 can each include its own counter for providing theappropriate addressing signals. Those of skill in the art willunderstand that counter 108 can, by example, be a 5-bit counter toprovide address signals for controlling 1 of 32 different column accesstransistors of the barrel shift decoder/multiplexing circuits 106 and107. In general, counter 108 can be an n-bit counter, where n isselected for the specific memory configuration to be used. The parityevaluator circuit 112 performs an exclusive OR function across theglobal databus GDB, and compares the result to the logic state of acolumn parity bit provided by the barrel shift decoder/multiplexingcircuit 107. In otherwords, parity evaluator circuit 112 detects thespecific bit position of the word that is the bad bit.

Each global databus line GDB is connected to the global databusinverting circuit 114 which is responsive to the GPFAIL output of theparity evaluator circuit 112 for inverting all the data carried by theglobal databus. Each global databus line is further connected to columnparity check circuit 116 for selectively changing bits of a columnparity word read from parity block 110 during a data word writeoperation. Details of column parity check circuit 116 are discussedlater.

Using the previously described example memory array configuration, ifeach memory block 52 has columns divided into 32 groups of 4 columnseach, then the set of parity columns 102 is at least one additionalgroup of columns. In the present example, parity columns 102 includes 4columns since each group of the block includes 4 columns. Accordinglyfor the present example, the first stage column access devices 54selectively couples one of the parity columns to the parity bit databus,which is in effect one complementary pair of datalines, and one columnfrom each group of columns to a respective local databus line. It isnoted that the number of cells per bitline, or column, does not impactthe scheme, and can be set by the desired cell-to-bit capacitance ratio.Accordingly, each memory block has 33 LDB pairs, and the entire ECCmemory system 100 has 32 GDB pairs. If the memory array includes 16memory blocks 52 plus the parity block 110, then 16 wordline segments(one segment per memory block) are gated from a master wordline. Thewordline segment length can be set by technology, e.g. the build-up ofpolysilicon line resistance. The number of segments in part determinesthe cell overhead as a parity wordline segment from the parity block 110will also be fed from the master wordline. The cell overhead for thepresently disclosed example is approximately 9%.

Examples of the error detection and purging memory system 100 shown inFIG. 4 will now be described.

FIG. 5 shows a circuit schematic example of the parity evaluator circuit104 shown in FIG. 4. Parity evaluator circuit 104 includes a serialparity chain 120 coupled to a comparator circuit 124. Each LDB pair isconnected to four n-channel transistors 126, 128, 130 and 132 withinserial parity chain 120. The serial parity chain 120 includes two paritylines 134 and 136, where one is connected to a high logic level signaland the other is connected to a low logic level signal at one endthereof. The four n-channel transistors 126, 128, 130 and 132 connectedto the two parity lines 134 and 136 perform a switch-over functiondepending upon the logic states of the local databus lines they areconnected. For example, LDB0 is at the high logic level and LDB0* is atthe low logic level, transistors 126 and 132 will be turned on whiletransistors 128 and 130 remain turned off. Hence HIGH is coupled to thenext set of four n-channel transistors connected to the next pair oflocal databus lines. Otherwise, transistors 126 and 132 will be turnedoff while transistors 128 and 130 are turned on if LDB0 is at the lowlogic level and LDB0* is at the high logic level. In this situation,parity line 134 is coupled to LOW and parity line 136 is coupled toHIGH. Hence HIGH and LOW propagate along parity lines 134 and 136, toappear as signals EVENPAR and ODDPAR at the inputs of comparator circuit124. Comparator circuit 124 then compares the logic states of EVENPARand ODDPAR to the logic states of the row parity bit provided via PDBand PDB*. The result of this comparison appears as signal LPFAIL. LPFAILis local to each memory block 52 and can be used to inform the systemthat a particular memory block 52 has encountered parity failure. Thoseof skill in the art will understand that any desired number of4-transistor sets of n-channel transistors can be used in serial paritychain 120. Furthermore, those of skill in the art will understand thatp-channel transistors and complementary transistor transmission gatescan be used in place of the n-channel transistors shown in FIG. 5.

FIG. 6 is a circuit schematic example of a circuit that can be used ascomparator circuit 124 in FIG. 5. Comparator circuit 124 includes astandard cross-coupled latch 140, also known as a sense circuit, parityline isolation devices 142 and 144, sense enable transistor 146, and acomparator logic, such as XOR gate 148. Input EVENPAR is connected totransistor 142 and input ODDPAR is connected to transistor 144, andtheir respective voltage levels are connected to comparator circuit 124when sense amplifier enable signal SAEN is at the low logic level.Comparator circuit 124 latches the logic levels of EVENPAR and ODDPARwhen SAEN falls to the high logic level, and the logic level of EVENPARis then XOR'd with the logic level of PDB by XOR gate 148. In thepresent example, comparator circuit 124 drives LPFAIL to the high logiclevel when local parity failure is detected. The present circuitcompares the logic state of one parity line with the logic state of onePDB line. In alternative embodiments, additional logic can be added tothe circuit of FIG. 6 to compare the presently unused output 145 ofsense circuit 140 to the unused PDB* dataline (not shown). Manydifferent sense circuits are known in the art that are suitable forsensing the voltage or current level of EVENPAR and ODDPAR, which can beused instead of the circuit shown in FIG. 6.

As will be discussed later, row parity circuit 104 can be used forgenerating a row parity bit corresponding to a written word. BecauseEVENPAR represents the parity of a word received by its serial paritychain 120 via the global databus and local databus, its output can bewritten back to its memory block 52. The comparator circuit of FIG. 6can be modified to include switching means, such as gating devices, toswitch PDB from the input of XOR gate 148 to the output of sense circuit140, and to disconnect the output of sense circuit 140 from the otherinput of XOR gate 148 during write operations.

In an alternate circuit configuration, the serial parity chain 120 canbe segmented to include sub-parity circuits. In otherwords, the paritylines 134 and 136 can be segmented and sensed by another latch circuit140, with the result being provided to the next segment. In thissegmented embodiment, the output of the sub-parity circuit latch drivesone of the parity lines of the next sub-parity circuit. This alternativeconfiguration can minimize the cumulative delay in the parity chain whencompared to a parity chain having non-segmented parity lines.

FIG. 7 shows a schematic and arrangement of the barrel shiftdecoder/multiplexor circuit 106 from FIG. 4. Two barrel shiftdecoder/multiplexor circuits 106 are shown in FIG. 4. The leftmostbarrel shift decoder/multiplexor circuit 106 includes column accesstransistors 150, 152 and 154, each controlled by a different columnaccess signal, such as YB0, YB1 and YBi. Column access signals aregenerated by decoder circuit 156, which receives local parity failsignal LPFAIL0, global parity fail signal GPFAIL and addresses ADDRprovided by the counter 108 of FIG. 4. Decoder circuit 156 activates onecolumn access signal at a time to sequentially couple each LDB pair toGDB0/*. The rightmost barrel shift decoder/multiplexor circuit 106 isidentical to the leftmost circuit, but receives a different local parityfail signal LPFAIL1 and sequentially couples each of its LDB pairs toGDB1/*. The column access devices are not shown in the rightmost circuitto simplify the schematic. Accordingly, the barrel shiftdecoder/multiplexor circuit 106 for each memory block 52 sequentiallycouples each of its LDB pairs to a different GDB pair.

As previously mentioned, all the GDB pairs are inverted when the globalparity circuit detects parity failure. Therefore, each decoder circuit156 has the ability to maintain its currently selected column accessdevice turned on. However, because only the memory block 52 having thelocal parity failure is to have its bad bit inverted, the LDB pairs ofthe memory blocks 52 without local parity failure are preferablydecoupled, or isolated, from their respective GDB pairs before all theGDB pairs are inverted when the global parity failure is detected. Hencethe local parity fail and global parity fail signals can be used tologically ensure that only the decoder circuit 156 associated with thememory block 52 having the local parity failure has its LDB pairinverted. Examples of circuits to perform this function are shown inFIGS. 9 and 10.

FIG. 8 shows a circuit schematic of a decoder circuit 156 that can beused in FIG. 7. In the present example, decoder circuit 156 receivescounter signals C1 to C4 and their complements, C1* to C4* to provide 1of 16 column access transistor selection, the global parity fail signalGPFAIL, and the local parity fail signal LPFAILn, for activating aspecific column access signal and keeping it activated when both GPFAILand LPFAILn are at logic levels indicative of parity failure. Thus thedecoder circuits 156 associated with memory blocks that do not have alocal parity failure will be deactivated.

A first NAND gate 180 receives counter signals C1, C2, C3 and C4 forproviding its output to inverter 182. NOR gate 184 receives input signalGPFAIL via inverter 192 and LPFAILn, and has its output inverted byinverter 186. NAND gate 188 receives the outputs of inverters 182 and186, and drives the input of inverter 190 for generation of columnaccess signal YB0. Additional column access signals are generated byidentical sub-circuits having the same configuration as gates 180 to190, but with different counter inputs. For example, second NAND gate180 receives counter signals C1*, C2, C3 and C4. It is noted thatLPFAILn is the local parity fail signal generated by a respective parityevaluator circuit 104, and is connected to the same NOR gate in eachsub-circuit. GPFAIL is the global parity fail signal generated by parityevaluator circuit 112 and is connected to the same NOR gate in eachsub-circuit of all decoder circuits 156 in ECC memory system 100. Thoseof skill in the art will understand that NOR gate 184 and inverter 186can be replaced by an equivalent NAND gate, and NAND gate 180 andinverter 182 can be replaced by an equivalent NOR gate to simplify theschematic and reduce component count.

The operation of decoder circuit 156 is now described. In the case wheredecoder circuit 156 is associated with a memory block 52 that does notreport local parity failure, LPFAILn remains at the low logic level aspreviously described for FIG. 8. Prior to the global parity check,GPFAIL remains at the low logic level to indicate the absence of aglobal parity failure. As will be described later, parity evaluatorcircuit 112 functions identically to previously described local paritycircuit 106. Therefore all NOR gates 184 of decoder circuit 156 driveinverter 186 with a low logic level, which in turn, drives an input ofNAND gate 188 to the high logic level. Now YB0 can be activated to turnon a corresponding column access transistor through the addresses C1,C2, C3 and C4 connected to NAND gate 180. The data of the LDB pairs arecoupled to the GDB pairs and the parity evaluator circuit 112 proceedsto check the global parity.

In the case where decoder circuit 156 is associated with a memory block52 that does report local parity failure, LPFAILn is driven to the highlogic level. Prior to the global parity check, GPFAIL remains at the lowlogic level to indicate the absence of a global parity failure.Therefore all NOR gates 184 of decoder circuit 156 drive inverter 186with a low logic level, which in turn, drives an input of NAND gate 188to the high logic level as in the previous case above. YB0 is activatedto turn on a corresponding column access transistor through theaddresses C1, C2, C3 and C4 connected to NAND gate 180. The data of theLDB pairs are coupled to the GDB pairs and the parity evaluator circuit112 proceeds to check the global parity.

However, decoder circuit 156 behaves differently in both described caseswhen global parity failure is detected. GPFAIL is driven to the highlogic level when global parity failure is detected. In the first casewhere there is no local parity failure (LPFAIL=Low), inverter 192 drivesits NOR gate inputs to the low logic level, which in turn drives aninput of NAND gate 188 to the low logic level. YB0 is then driven to thelow logic level to turn off the previously turned on column accesstransistor. In the second case where there is local parity failure(LPFAIL=High), the changing state of GPFAIL has no effect upon theoutput of NOR gate 184 since LPFAILn is already at the high logic level.Hence YB0 remains active and its previously turned on column accesstransistor remains turned on. Now when the GDB pairs are inverted due tothe detected global parity failure, only the LDB pair coupled to the GDBpair has its data inverted. The data of the LDB pair can then be writtento memory as previously described. Collectively, the decoder circuits156 permit exactly one column access transistor across all the memoryblocks to be activated.

FIG. 9 shows a circuit schematic of the parity evaluator circuit 112shown in FIG. 4. Parity evaluator circuit 112 is identically configuredto the circuit of FIG. 5 except for the input signals connected to it.The components of parity evaluator circuit 112 having the same referencenumerals as those same components in FIG. 5 have already been describedand hence do not require further description. Specifically, GDB pairsare connected to the four n-channel transistors 126, 128, 130 and 132within serial parity chain 120, and comparator circuit 124 compares thelogic states of EVENPAR and ODDPAR to the logic states of the columnparity bit provided via parity block databus lines PBBIT and PBBIT*. Theresult of this comparison appears as signal GPFAIL. GPFAIL can be aglobal signal used in each memory block 52 and can be used by the systemto initiate other system processes, such as for activating globaldatabus inverting circuit 114. In the present example, comparatorcircuit 124 drives GPFAIL to the high logic level when global parityfailure is detected.

FIG. 10 is a circuit schematic showing global databus inverting circuit114 connected to the GDB. To simplify the schematic, only twocomplementary global databus and associated flip-flop circuits 200 areshown, but those of skill in the art will understand that there is oneflip-flop 200 for every global databus pair. The global databusinverting circuit 114 has the function of inverting the state of datacurrently on the GDB in response to a control signal, which ispreferably the global parity fail signal GPFAIL. The global databusinverting circuit 114 includes a plurality of standard D-type flip-flops200, where each flip-flop 200 is connected to one GDB pair. Eachflip-flop has a D-input for receiving data, a clock input for receivinga control signal, a Q-output for providing true data and a Qb-output forproviding the complement of the data. In the present example, therightmost flip-flop 200 receives a data signal from GDB0* and has itsQ-output connected to GDB0 and its Qb-output connected to GDB0*. Theleftmost flip-flop 200 is arranged in the same configuration with GDB1/*as the rightmost flip-flop 200 is with GDB0/*. Both flip-flops 200receive clocked parity fail signal GPFAIL provided by parity evaluatorcircuit 112. While D-type flip-flops are used in the present embodiment,other types of flip-flop circuits well known to those of skill in theart can be used instead.

A description of the operation of global databus inverting circuit 114follows with reference to the rightmost flip-flop 200. GPFAIL isinactive at the low logic level when there is no global parity failuredetected and data from GDB0* is latched but prevented from being drivenonto the Q and Qb output terminals. When GPFAIL rises to the high logiclevel after parity evaluator circuit 112 detects global parity failure,the latched true data from the D-input is driven onto GDB0 and thecomplement of the data is driven onto GDB0*. Accordingly, the data onall global databus lines are inverted by global databus invertingcircuit 114. As previously noted, the decoder circuits 156 of the memoryblocks 52 that do not have local parity failure prevent the inverteddata of the global databus to be written back.

The method for performing error detection and correction with thearchitecture described and shown in FIGS. 4 to 10, follows withreference to the flow chart of FIG. 11. It is assumed that data has beenwritten into the memory array and the parity bits have been generatedand stored. It is further assumed that a master wordline and allwordline segments coupled to the master wordline are activated during aread/refresh operation, and the word being accessed in memory block0contains a faulty bit of data. The process for generating and storingthe parity bits is discussed later.

Initiation of the error detection and correction process begins with arefresh or read operation in step 300. This involves activation of themaster wordline and corresponding wordline segments of each memory blockwithin the memory array. Hence the sense amplifiers of each memory blockare loaded with data. Column decoders control the first stage columnaccess devices 54 to couple one of the 4 bitlines of each group to eachof the associated 32 LDB pairs, and the corresponding parity bitline toits parity bit databus pair.

In step 302, a parity check of the LDB against PDB is performed by theparity evaluator circuits 104 of each block, with the respective LPFAILnoutput carrying the logical result of the parity check, representing theparity of the 32 bit word. If at step 304 there is no parity failuredetected, as indicated by a logic “0” level for example, then the errordetection and correction process ends and a normal read operationproceeds. If the process was initiated by a refresh operation, thenanother row segment refresh cycle can be executed.

If row parity failure is detected in memory block0 for example, theerror is flagged via local parity fail signal LPFAIL0 and the systemalerted that there is bad data, but good data will be available afterpurging is complete. In this particular example, the local paritycircuit can generate a local parity fail signal for later use as acontrol signal and to indicate that the 32 bit word of that particularblock has an error.

A barrel shift operation begins at step 306 to couple the same logicalbit position from each set of LDB's to a global databus line. Forexample, the bit from LDB0 of memory block 0 is coupled to GDB0, the bitfrom LDB0 of memory block 1 is coupled to GDB1 etc, such that the GDBcarries all the 0 position bits from each memory block in a firstiteration. The 0 position bit from the LDB's of the parity block is alsoprovided in the same iteration. It is noted that data from the currentrefresh or read cycle is preferably maintained in the bitline senseamplifiers to avoid having to repeat read out of data. Hence it ispreferable to use a DRAM architecture in which an equalize/prechargeoperation immediately precedes the active cycle rather than after theactive cycle is finished.

In step 308, the parity evaluator circuit 112 determines the parity ofthe GDB's and compares the result with the column parity bit from theparity block. If no parity failure is detected in step 310, the processproceeds to step 312 where the counter 108 is incremented so thatanother barrel shift iteration can proceed in step 306 for the next bitposition.

However, if parity failure is detected in step 310, an error flag GPFAILis generated and the process proceeds to step 314. Therefore, it hasthus been determined that the error has occurred in the present bitposition being checked. For example, if the parity failure occurredduring a check of all the “0” bit positions, then it is known that bitposition “0” of the word with the error is bad.

In step 314, GDB inverting circuit 114 is activated to invert all thedata bits of the GDB when global parity failure has been detected viaGPFAIL. Because decoder circuit 156 of block0 has LPFAIL0 at the logic“1” level, only its column access signal remains activated. The decodercircuits 156 for all the other blocks having GPFAIL at the logic “1”level and their LPFAILn signals at the logic “0” will have their columnaccess signals disabled. Thus only the LDB belonging to the memory blockflagged with the local parity failure remains coupled by the LPFAIL0flag to its corresponding GDB via its barrel shift decoder/multiplexor106. Hence just the data of the one LDB is inverted, as is the column itis coupled to. The error is purged and the corrected data is restored inthe memory block. It should be noted that for the current iteration, thecolumn decoders and the counter 108 for controlling the first stagecolumn access devices 54 and the barrel shift decoder/multiplexor 106have not changed since reading out the data for which the row parityfailed. Hence the data path to the erroneous column remains active. Thememory blocks 52 that did not have the row parity failure will not havegenerated their own local parity fail signal. Therefore, the barrelshift decoder/multiplexor circuits of these memory blocks willdeactivate and prevent the GDB's from asserting the inverted data ontotheir respective LDB's.

Once the global parity failure has been detected and corrected, theprocess can terminate. Optionally, the process can loop back to step 312so that the next bit position of the LDB's is coupled to the GDB's forthe column parity check in the subsequent iteration. This optional stepcan be implemented to detect and correct multiple bit failures.

While the presently described method is applicable to memoryarchitectures where all wordline segments associated with a masterwordline are activated during a read operation, an alternate embodimentof the presently described method is applicable to memory architectureswhere only one wordline segment associated with a master wordline isactivated during a read operation. This is a type of low power memoryarchitecture in which memory blocks that are not accessed do not consumebitline and sense amplifier power. However, refresh operations stillrequire activation of all wordline segments associated with the masterwordline.

Therefore, in the method according to an alternate embodiment of thepresent invention, a parity failure detected during read out of datafrom a single memory block, where only that wordline segment isactivated, will initiate a refresh operation to activate all thewordline segments of the currently activated master wordline. Tominimize peak power consumption, it is preferable to stagger activationof the wordline segments in a manner well known to those of skill in theart. Once all the wordline segments have been activated, as in a refreshoperation in step 300 of FIG. 11, steps 302 to 314 of the method shownin FIG. 11 can proceed to identify the specific bit position of the wordto be purged.

The method shown in FIG. 11 is ideally suited for memory architecturesthat activate all wordline segments of a master wordline during readoperations, however, the addition of the previously discussed precedingsteps for operating the device in a refresh mode adapts the method formemory architectures that activate only one wordline segment during aread operation.

Therefore, soft errors can be purged during refresh operations in whichdata is read out to the LDB pairs of each memory block 52, before thenext read/refresh cycle is executed. System cycles can be consumedwithout impacting read performance since no system operation such as aread operation is being delayed. Now errors cannot build up because aread operation has not been executed. However, soft errors can stilldevelop within the period of time between a current read operation and aprevious refresh cycle. In such a situation, the error can be flaggedand a “wait” required while the error is purged by the serial globalparity check process. Because the global parity check is performedserially, only a single set of circuits are required, which reducesoverhead, lowers power consumption and use of silicon area versus ECCarchitectures in which column parity checks are done in parallel.

The previously described circuits of ECC memory system 100 are examplesof suitable circuits for executing the error detection and purgingmethod described in the flow chart of FIG. 5. A desired advantage of theembodiment of ECC memory system 100 shown in FIG. 4 is the absence ofany additional wide bussing that is currently used in ECC systems of theprior art for carrying corrected data from the global parity checkcircuit back to the memory blocks 52. The embodiment of the ECC memorysystem 100 shown in FIG. 4 avoids the use of additional wide bussing byre-using the global data buses and local data buses that are alreadyinherently necessary for normal memory read and write operations. Theaddition of simple circuits coupled to the local and global databusprovides this additional functionality for the local and global databus.

It should be noted that memory system 100 can be limited to include onlythe row parity circuits 104 for detecting an error in the word beingread out. In such a configuration, locating and correcting the erroneousbit position of the word can be determined by an external system, suchas a microcontroller block for example. Specifically, the externalsystem can read out the required data from memory system 100, correctthe bad bit and rewrite the corrected word back into memory system 100using any one of a variety of well known data correction techniques. Inthe present circuit, the flag signal LPFAIL can signal the externalsystem to initiate error purging operations. Furthermore, as row paritycircuit 104 has the capability to generate and write a row parity bit inparallel with a word being written, write operations can proceed quicklyand automatically.

It should be further noted that the column parity circuit embodiments ofthe present invention use as many global dataline pairs as there arememory blocks for storing words. For example, if the global databus is16 bits wide, and there are eight memory blocks 52 in memory system 100,only eight global databus line pairs are used during the column paritycircuit operation. In particular, only those global dataline pairsconnected to a barrel shift decoder/multiplexor circuit 106 areconnected to the parity evaluator circuit 112 for column parityevaluation. Accordingly, if memory system 100 has more memory blocks 52than available global dataline pairs, then additional dedicated datalinepairs can be included to receive the data from the barrel shiftdecoder/multiplexor circuits 106 of the ‘excess’ memory blocks.

The previously discussed embodiments of the present invention fordetecting and purging faulty bits relies upon the use of row and columnparity bits in order to determine the occurrence and location of afaulty bit of data. Since bits of data can be changed during writeoperations, the corresponding row and column parity bits may no longercorrectly reflect the parity of the new data. While these parity bitscan be generated off chip, or in a processor block of an ASIC device,and subsequently written directly to the parity columns 26 and theparity block 110, the additional circuit and processor cycle overhead toread out data and write in parity data renders such schemes impractical.Therefore, it is preferable to generate the parity bits locally withinthe domain of the memory circuits since the data required for generationof parity bits resides in the memory blocks.

According to an embodiment of the present invention, row and columnparity bits can be generated within memory system 100, and written tothe parity column 102 and parity block 110 respectively, as data isbeing written. However, it is important to note that the logic states ofthe row and column parity bits is dependent upon known states of data.While generation of a row parity bit corresponding to a newly writtenword of data can be executed in a straightforward manner, as will bedescribed later, generating a corresponding column parity bit requiresthat the logic states of words of data associated with the sameactivated wordline are effectively known. Since memory cells storerandom data upon power up, it is necessary to initialize all the memorycells to a known state prior to any write operation.

According to another embodiment of the present invention, all the memorycells of the memory system 100 are initialized to a “0” logic state suchthat all words are set to the null (logic “0”) state, and the logic “0”state of all row and column parity bits will correctly reflect theparity of null words stored in the memory blocks. Alternatively, all thememory cells of the memory system 100 can be initialized to a “1” logicstate.

FIG. 12 is a flow chart illustrating a method of initializing the memorycells of memory system 100 according to an embodiment of the presentinvention. Assuming that a traditional power up sequence has beencompleted to initialize the circuits, the memory initialization sequenceof FIG. 12 can commence at step 400. At step 400, “0” logic data iswritten to the memory cells of an activated wordline via a typical writeoperation. While one word is written during a typical write operation,according to the present embodiment, all the first and second stagecolumn access devices 54, 58 of all memory blocks 52, 110 can besimultaneously activated to couple the “0” logic data presented on theglobal data bus to every column of each memory block 52, 110simultaneously. Those of skill in the art will understand that thecolumn decoder circuits can be configured to simultaneously activate allaccess devices under the control of a single “activate all” controlsignal. After the “0” logic state is written to all the memory cellscoupled to the active wordline, a read access of the cells coupled tothe previously written wordline is performed at step 402 to load/latchall the bitline sense amplifiers with the “0” logic state data. Thebitline precharge and equalize circuits are then disabled in step 404 inpreparation for step 406. Using existing refresh counters that controlwordline activation, each wordline is iteratively activated to coupleits memory cells to the bitline sense amplifiers via bitlines. With thebitline sense amplifiers latching the “0” logic state, the memory cellswill be restored, or re-written, with “0” logic data. Because all thebitline sense amplifiers of each memory block 52, 110 have latched the“0” logic state in step 402, the refresh counter only needs to cycleonce through all the wordlines. Those of skill in the art willunderstand that the bitline precharge and equalize circuits are disabledduring the presently described refresh operation to ensure that thebitline sense amplifiers overwrite the bitline voltage potentialintroduced by the memory cells. Techniques for disabling the bitlineprecharge and equalize circuits should be well known to those of skillin the art.

While the presently described embodiment writes the logic “0” level toall the cells of an activated wordline in step 400, multiple writeoperations can be executed to successively write null value words to thesame wordline by maintaining the same row address while changing columnaddress in each cycle. Those of skill in the art will understand thatother methods can be devised to write the logic “0” state to the initialactivated wordline, and that the current method can be adapted fordifferent memory configurations. Of course, the memory initializationsequence of FIG. 12 is not limited to being executed as part of a powerup reset sequence, and can be executed at any time it is desired toclear the memory of its contents. As the memory initialization sequenceof the present embodiment is directed to DRAM memory, alternateembodiments can be directed to different types of memories with theappropriate variations to account for the specific technology involved.For example, standard SRAM does not require refresh operations, hencethe wordlines can be activated through external address control.

After the memory blocks 52, 110 have been initialized, write operationscan proceed, with automatic generation and writing of row and columnparity bits corresponding to the written words. A method for generationand writing of row and column parity bits according to an embodiment ofthe present invention is shown in FIG. 13.

Generally, the method of FIG. 13 defines a single write operation forthe memory system 100 shown in FIG. 4 that automatically generates a newcorresponding row parity bit and selectively modifies correspondingcolumn parity bits as required, when new data is written. Specifically,each bit of the newly written word is compared to each corresponding bitof the currently stored word to determine if there is a change in thelogic state of the bit in the new word. A change in logic state changesthe logic state of the corresponding currently stored column parity bitfor that bit position. The present method makes use of the memorycircuit infrastructure to minimize the addition of bus lines. Thepresently described method only examines the bits of the written word todetermine if column parity bits need to be changed, and does not requirecumbersome reading of the associated words that collectively define thestate of each column parity bit.

The write operation starts at step 500 with a read access, where the rowaddress to be written to is accessed and the current word stored thereinis read out to the global databus. A column parity check circuit havinga first set of registers coupled to the global databus latches the datafor use in a subsequent step. It is noted that the data on the globaldatabus does not proceed to the output path circuits as this is not atrue read operation.

At step 502 the new word data is asserted onto the global databus andwritten to the addressed memory block. A second set of registers of thecolumn parity check circuit coupled to the global databus latches thedata for use in a subsequent step.

In step 504, the parity evaluator circuit 104 coupled to the LDB willgenerate an output from sense amplifier 140 of FIG. 6 reflecting the rowparity of the LDB data being written to the memory block 52. Morespecifically with reference to FIGS. 6 and 7, additional logic can beadded to disable XOR gate 148 during write operations, and gating logiccan be added to couple the outputs of cross-coupled latch 140 to PDB andPDB* during write operations. This logic adds minimal circuitry to eachparity evaluator circuit 104, and can be implemented with well knowncircuits configured in a manner known to those of skill in the art.

At step 506, each bit position stored in the first and second set ofregisters are compared to each other to determine if a bit of the newword is the same or different than the corresponding bit of the oldword. A flag indicating a match or mismatch of the comparison can be setfor each bit position in step 506.

Proceeding to step 508, the corresponding parity word is accessed fromparity block 110 and read out onto the global databus. It is noted thatthe old word read out in step 500, the new word written in step 502, andthe parity word of the present step are activated by the same wordlineaddressed in the current write operation. Each bit position of theparity word represents column parity for that bit position of all wordsin the other blocks 52 accessible by the same row and column address.

In step 510, the flags set in step 506 are used to activate invertingcircuits of the column parity check circuit coupled to the globaldatabus. Any inverting circuit receiving a flag will invert the data onits corresponding databus line in step 512, and any inverting circuitthat does not receive the flag will not change the data on itscorresponding databus line, ending the process at step 514. Any changesto the global databus are propagated back to the parity block 110, wherethose bitlines coupled to changed global databus lines rewrite the dataof its corresponding memory cell.

As previously mentioned, parity evaluator circuits 104 that are used tocheck parity of a word that is read out can be used to generate thecorresponding row parity bit as the new word is written to its memoryblock 52. The comparator circuit of FIG. 6 can be modified to includegating devices to switch PDB from the input of XOR gate 148 to theoutput of sense circuit 140, and to disconnect the output of sensecircuit 140 from the other input of XOR gate 148 during the writeoperation. A circuit embodiment of a column parity check circuit thatcan be used in accordance with the method of FIG. 13 is shown in FIG.14.

The column parity check circuit embodiment of FIG. 14 is coupled to theglobal databus for comparing old stored data words to new write datawords, and selectively inverting the datalines corresponding to bitpositions having mismatching data. Column parity check circuit 116includes a parity comparison circuit 602 and a parity inverting circuit604. The parity comparison circuit 602 latches an old stored data wordand a new write data word, and provides flag signals indicative of amismatch between individual bit positions. The parity inverting circuit604 inverts global datalines in response to received flag signals. Twoglobal dataline pairs and corresponding circuits are shown in FIG. 14 toillustrate the circuit configuration of the column parity check circuit,however, any person of skill in the art should understand that thepresently shown circuit embodiment can be scaled to accommodate anynumber of global dataline pairs.

Parity comparison circuit 602 includes a first set of GDB registers 606that are each connected to receive and latch a respective globaldataline logic level in response to a first clock signal CLK1, and asecond set of GDB registers 608 that are each connected to receive andlatch a respective global dataline logic level in response to a secondclock signal CLK2. Each first register 606 and second register 608receiving the same global dataline signal form a comparison pair, andtheir outputs are provided to an associated XOR gate 610. An AND logicgate 612 associated with each comparison pair receives the output of aXOR gate 610, and passes the XOR gate 610 output in response to clocksignal CLK3.

Parity inverting circuit 604 includes D-type flip-flops 614 having theirinputs and outputs connected to the global datalines in a configurationsimilar to global dataline inverting circuit 114 shown in FIG. 10. Theclock input of flip-flops 614 receive an output from AND gate 612 toreceive and latch respective global dataline signals.

The operation of column parity check circuit 116 is now described withreference to the steps described in FIG. 13. It is assumed that all theclock signals CLK1, CLK2 and CLK3 are presently inactive. The first setof GDB registers 606 latch the data accessed from the addressed locationin step 500, in response to an active CLK1 signal. Thus the Q-output ofeach register 606 is provided to an input of associated XOR gate 610.Subsequently, the second set of GDB registers 608 latch the new data tobe written to the addressed location in step 502, in response to anactive CLK2 signal. The Q-output of each register 608 is provided to theother input of the associated XOR gate 610. The active level output ofeach XOR gate 610 can be considered the flag indicative of a mismatch.In the present example, the active level is a high logic level if theQ-outputs of the comparison pairs are at different logic levels. Theparity block word is read out to the global datalines in step 508, andCLK3 is set to the active level to pass the output of each XOR gate 610to registers 614. Any flip-flop register 614 receiving an active XORgate 610 output will latch and invert the data of its correspondingdataline pair. Conversely, any flip-flop 614 that does not receive anactive XOR gate 610 output will not latch and invert its dataline pair.CLK1, CLK2 and CLK3 are activated in sequence and with sufficient delaybetween each other to allow the global dataline pairs to be properlyreset and stabilize with data. The first and second stage column accessdevices 54, 58 associated with parity block 110 can remain active toallow the changed logic states of the global dataline pairs to propagateback to the memory cells. After the bits of the parity block word arewritten back to memory, the activated wordline is deactivated, and thewrite operation is completed. Therefore, new row and column parity bitscan be generated automatically and independent of any systems externalto the embedded memory in response to new data being written to memorysystem 100. The memory system 100 can be controlled by write controlcircuits (not shown) that can be implemented by any person of skill inthe art.

The error correction and purging scheme disclosed is well suited toincorporation in embedded DRAM systems to reduce cell size and costwhile simultaneously increasing robustness against soft errors or randommiss-reads. Fault tolerance is further improved by incorporating wellknown redundancy techniques to replace defective memory cells with newmemory cells, and then using the error correction and purging system ofthe present invention to correct soft errors that may occur in eitherthe normal memory cells or the new memory cells. Adding redundancy tothe memory configuration shown in the figures should be straight forwardto those of skill in the art. For example, extra rows are completelyindependent, and a 4-column data bus strip for each segment can bemapped in a straightforward manner. Furthermore, the single bit rowparity bit is independent of word length and the single bit columnparity bit is independent of the number of words associated with thesame master wordline, unlike Hamming code error correction schemes wherethe required number of error correction bits depends upon the wordlength.

While the previously described embodiments of the present invention aredirected to DRAM, and in particular embedded DRAM, they can apply toother types of memories such as SRAM, ferro-electric RAM (FeRAM), andother non-volatile memories. These alternate memories are alsosusceptible to bit errors, and can benefit from automatic errordetection, purging and parity bit generation. As should be obvious toone of skill in the art, circuits and control algorithms specific to atype of memory and its architecture can be adapted to integrate theerror correction and purging techniques disclosed. For example, sinceSRAM does not require refreshing operations, a data purge operation canbe periodically executed to initiate a ‘refresh-type’ operation tosearch and correct bad bits in the memory. Accordingly, the data wordcan be suppressed from global I/O circuits to prevent the data word fromappearing on an I/O pad or output line. Alternatively, once row parityfailure has been indicated, the external system can ignore the data wordpresented on its output. For non-volatile memories, re-writing correcteddata to the memory cells will require application and control of biasvoltages to inject or remove charge from floating gates of the memorycells.

Minimal additional silicon area is used by the parity circuit and columnparity check circuit embodiments of the present invention because theyare formed in the local and global databus routing areas, and the sizeof the global parity circuit is minimized because the global paritycheck is performed serially with one set of circuits. The performanceimpact of the ECC circuits is minimal because errors can be detected andpurged during refresh cycles in addition to read cycles. Hence theproblem of errors building up while data is stored but not accessed iseffectively eliminated, and read operations can be executed without anysignificant performance penalty. Furthermore, the ECC scheme embodimentof the present invention allows for repair of hard faults by traditionalredundancy techniques with minimal design overhead.

Enhanced reliability and lower cost is achieved through use of the errorcorrection and purging scheme embodiments of the invention, as memorycells can be deliberately arranged to store data with very little chargeand thus high susceptibility to soft errors or simple miss-reads after alonger period between refreshes. Additionally, lower power consumptioncan result from the use of longer refresh intervals.

The above-described embodiments of the present invention are intended tobe examples only. Alterations, modifications and variations may beeffected to the particular embodiments by those of skill in the artwithout departing from the scope of the invention, which is definedsolely by the claims appended hereto.

1. A method of detecting and purging bit errors in a memory, comprising:a) executing a read operation for providing a data word to a localdatabus and for providing a corresponding row parity bit, from a memoryblock of the memory; b) comparing row parity of the data word on thelocal databus against the corresponding row parity bit and generating arow parity fail flag in response to row parity failure; c) iterativelymultiplexing bits of the data word from the local databus onto acorresponding global dataline for comparing column parity of each bit ofthe data word against a corresponding bit of a column parity word storedin a parity block of the memory, in response to the row parity failflag; and, d) inverting bits of the data word that fail column parity.2. The method of claim 1, wherein the step of executing includessuppressing the data word from global I/O circuits.
 3. The method ofclaim 1, wherein the step of comparing row parity includes executing arow parity check of the local databus against the corresponding rowparity bit.
 4. The method of claim 1, wherein the step of comparingcolumn parity includes executing a column parity check of the globaldatalines against a corresponding column parity bit in each iteration.5. The method of claim 4, wherein the step of comparing column parityincludes inverting the data bits of the global datalines if columnparity failure is detected in each iteration.
 6. The method of claim 5,wherein the step of inverting includes inverting the data bit of a localdatabus line coupled to one of the global data lines for purging the biterror of the data word stored in the memory block.
 7. The method ofclaim 1, wherein the background read operation includes a refreshoperation.
 8. The method of claim 1, wherein the background readoperation includes a data purge operation.
 9. The method of claim 1,wherein the step of iteratively multiplexing includes selectivelyactivating column access transistors for coupling a different localdatabus line to the corresponding global dataline in each iteration. 10.The method of claim 1, wherein the step of selectively activatingincludes incrementing a counter to address and activate a differentcolumn access transistor in each iteration.
 11. The method of claim 10,further including maintaining activation of the column access transistorcorresponding to the memory block having row parity failure.
 12. Anerror detection and purging system for a dynamic random access memorycomprising: a plurality of memory blocks for storing data words andcorresponding row parity bits, one of the memory blocks being a parityblock for providing a column parity word; a local data I/O circuitcoupled to each memory block for transferring the data words to globaldatalines; a row parity circuit coupled to the local data I/O circuit ofeach memory block for receiving the data words and the corresponding rowparity bits in a memory block access operation, and for comparing parityof the data words against the corresponding row parity bits forgenerating a corresponding active local parity fail flag in response torow parity failure; and, a column parity circuit coupled to all thelocal data I/O circuits, the global datalines, and the parity block forreceiving the data words and the column parity word, the column paritycircuit iteratively transferring a bit from each of the data words to adifferent global dataline for comparing parity of the global datalinesto a corresponding bit of the column parity word, the column paritycircuit inverting data of the global datalines in response to columnparity failure in each iteration.
 13. The error detection and purgingsystem of claim 12, wherein each row parity circuit includes a serialparity chain for receiving the data word from the local data I/O circuitand for providing a parity output corresponding to parity of the dataword, and a sense circuit for receiving the parity output and thecorresponding row parity bit, for providing the active local parity failflag if the parity output and the corresponding row parity bit mismatch.14. The error detection and purging system of claim 13, wherein theserial parity chain includes an even parity line driven to a first logiclevel at one end, and an odd parity line driven to a second logic levelat one end, the parity output being provided from the other end of theeven parity line, and each parity circuit includes cross-overtransistors for coupling the parity output to one of the first andsecond logic levels.
 15. The error detection and purging system of claim14, wherein the sense circuit includes a cross-coupled latch forreceiving and latching the parity output, and a comparator circuit forcomparing the latched parity output to the local row parity bit.
 16. Theerror detection and purging system of claim 15, wherein the comparatorcircuit includes an exclusive OR gate.
 17. The error detection andpurging system of claim 12, wherein each memory block includes one ofredundant rows and columns, and corresponding redundancy circuits. 18.The error detection and purging system of claim 12, wherein the parityblock has a configuration identical to that of each memory block, and aparity block data I/O circuit for coupling bits of the column parityword to the column parity circuit.
 19. The error detection and purgingsystem of claim 18, wherein the column parity circuit includes amultiplexor circuit coupled between each local data I/O circuit and theglobal datalines for receiving the bits of the data word and foriteratively providing each bit of the data word to the global datalines,a parity block multiplexor circuit coupled to the parity block data I/Ocircuit for receiving the bits of the column parity word and forproviding one bit of the column parity word in each iteration, a parityevaluator circuit coupled to the global datalines and for receiving theone bit of the column parity word, the parity evaluator circuitcomparing parity of the global datalines to the one column parity bit ineach iteration and generating an active global parity fail flag inresponse to column parity failure, and a global dataline invertingcircuit for receiving and inverting data of the global datalines inresponse to the active global parity fail flag.
 20. The error detectionsystem of claim 19, wherein the multiplexor circuit and the parity blockmultiplexor circuit each include a counter.
 21. The error detection andpurging system of claim 19, wherein the global dataline invertingcircuit includes a flip-flop having an input coupled to one globaldataline, an output coupled to a complementary global dataline of theone global dataline, a complementary output coupled to the one globaldataline, and a clock input for receiving the active global parity failflag.
 22. The error detection and purging system of claim 12, furtherincluding a column parity check circuit for selectively changing bits ofthe column parity word on the global datalines in a write operation, forwriting a new word to an address of the data word stored in the memoryblock, the column parity check circuit including, a parity comparisoncircuit for storing the data word and the new word and comparing eachbit position of the stored data word to each corresponding bit positionof the stored new word, the parity comparison circuit providing amismatch flag signal for each bit position having mismatching logicstates, and a parity inverting circuit coupled to the global datalinesand for receiving the mismatch flag signals, the parity invertingcircuit inverting the logic state of the global datalines in response tothe corresponding received mismatch flag signals.